Sasha Fratini

static void scTaskAlertCallback(void) {
  static uint8_t packet[4];
  static uint8_t packetIndex = 0;

  scifClearAlertIntSource();

  uint32_t count = scifUartGetRxFifoCount();
  while (count > 0) {
    uint8_t b = (uint8_t)scifUartRxGetChar();
    count--;

    if (packetIndex == 0) {
      if (b == 0xFF) {
        packet[0] = b;
        packetIndex++;
      }
    } else {
      packet[packetIndex++] = b;
      if (packetIndex == 4) {
        if (((packet[0] + packet[1] + packet[2]) & 0xFF) == packet[3]) {
          scSensorPayload[0] = packet[1];
          scSensorPayload[1] = packet[2];
          scSensorPayload[2] = 0;
          scSensorPayload[3] = 0;
          scSensorPayload[4] = 0;
          Event_post(syncEvent, SBP_SC_ALERT_EVT);
        }
        packetIndex = 0;
      }
    }
  }

  scifAckAlertEvents();
  scifOsalEnableTaskAlertInt();
}

LL_TIM_WriteReg(TIM3, CR1, LL_TIM_ReadReg(TIM3, CR1) | 0x0001);
LL_TIM_WriteReg(TIM3, CCR2, 40);
LL_TIM_WriteReg(TIM3, CCR1, 200);

while (1)
{
  if ((LL_TIM_ReadReg(TIM3, SR) & 0x0002) == 0x0002) {
    LL_TIM_WriteReg(TIM3, SR, LL_TIM_ReadReg(TIM3, SR) ^ 0x0002);
    LL_GPIO_WriteReg(GPIOA, ODR, LL_GPIO_ReadReg(GPIOA, ODR) ^ 0x0400);
    LL_TIM_WriteReg(TIM3, CCR1, LL_TIM_ReadReg(TIM3, CCR1) + 200);
  }
  if ((LL_TIM_ReadReg(TIM3, SR) & 0x0004) == 0x0004) {
    LL_TIM_WriteReg(TIM3, SR, LL_TIM_ReadReg(TIM3, SR) ^ 0x0004);
    LL_GPIO_WriteReg(GPIOB, ODR, LL_GPIO_ReadReg(GPIOB, ODR) ^ 0x0400);
    LL_TIM_WriteReg(TIM3, CCR2, LL_TIM_ReadReg(TIM3, CCR2) + 40);
  }
}

//ENABLE DELL ADC e SWSTART
LL_ADC_WriteReg(ADC1, CR2, LL_TIM_ReadReg(ADC1, CR2) | 0x1);
LL_ADC_WriteReg(ADC1, CR2, LL_TIM_ReadReg(ADC1, CR2) | (1 << 30));
//ENABLE TIM3
LL_TIM_WriteReg(TIM3, CR1, LL_TIM_ReadReg(TIM3, CR1) | 0x0001);

while (1)
{
  // Controlla il bit EOC (End Of Conversion)
  int eoc = LL_ADC_ReadReg(ADC1, SR) & 0x0010;
  if (eoc == 0x0010) {
    // Azzeramento del bit EOC
    LL_ADC_WriteReg(ADC1, SR, LL_ADC_ReadReg(ADC1, SR) | 0x0010);
    // Leggi il valore dal registro dati dell'ADC
    double ridden_value = LL_ADC_ReadReg(ADC1, DR);
    newRef = ((-0.04675*ridden_value)+ 14.374) * ridden_value;
  }
  if ((LL_TIM_ReadReg(TIM3, SR) & 0x0002) == 0x0002) {
    //toggle PB10
    LL_GPIO_WriteReg(GPIOB, ODR, LL_GPIO_ReadReg(GPIOB, ODR) ^ 0x0400);
    //Aggiorno soglia OUTPUT COMPARE
    LL_TIM_WriteReg(TIM3, CCR1, LL_TIM_ReadReg(TIM3, CCR1) + newRef);
    //Azzero il bit 1 dello state register
    LL_TIM_WriteReg(TIM3, SR, LL_TIM_ReadReg(TIM3, SR) & 0xFFFD);
  }
}

HAL_TIM_IC_Start_IT(&htim3, TIM_CHANNEL_1);
HAL_TIM_PWM_Start(&htim4, TIM_CHANNEL_1);

void HAL_TIM_IC_CaptureCallback(TIM_HandleTypeDef *htim) {
  static last = 0;
  int current;
  if (htim == &htim3) {
    current = htim->Instance->CCR1;
    if (last <= current) {
      period = current - last;
    }
    else {
      period = 65535 - last + current;
    }
    last = current;
    freq = 1/(period/(84*1e4));
    int newDC = 41 + ((freq / 280 )- 22.857);
    newDC = ceil(newDC);
    __HAL_TIM_SET_COMPARE(&htim4, TIM_CHANNEL_1, newDC);
  }
}

--CLOCK MANUALE
clk <= KEY(1);
resetn <=KEY(0);

--SALVA NEI REGISTRI D INGRESSO
regA : regn port map (signed(SW(127 downto 64)), clk, resetn, A_sign);
regB : regn port map (signed(SW(63 downto 0)), clk, resetn, B_sign);

A <= std_logic_vector(A_sign);
B <= std_logic_vector(B_sign);

-- Initialize Co(0)
Co(0) <= '0';

--SOMMATORE
sommatore : FOR i IN 0 TO 63 GENERATE
  full_adder_temp: full_adder PORT MAP (Co(i), A(i), B(i), S(i), Co(i+1));
END GENERATE sommatore;

--SALVA IN REGISTRO FINALE
regS : regn port map (signed(S),clk, resetn, uscita_sign);
uscita <= std_logic_vector(uscita_sign);

overflow <= Co(64) xor Co(63);

flip_flop0: flipflop PORT MAP (overflow, clk, resetn, v);

TYPE state_type is (H, E, L,L_0, O, B);

reg0: regn port map (serial_in, clock_local, reset_local, reg_out(2 downto 0));

registri: for i in 1 to 5 generate
reg: regn port map(reg_out((3*i)-1 downto (3*i)-3), clock_local,
                   reset_local, reg_out((3*i)+2 downto 3*i));
end generate;

process(clock_local,reset_local)
Begin
  --reset asincrono
  if(reset_local = '0') then
  current_state <= H;

  elsif(Clock_local'EVENT AND Clock_local = '1') then

  case current_state is
    when H => current_state <= E;
    when E => current_state <= L_0;
    when L_0 => current_state <= L;
    when L => current_state <= O;
    when O => current_state <= B;
    when B => current_state <= H;
  END CASE;
  END IF;
End process;

-- Codes emitted by hello_fsm: H=001, E=010, L=011, O=100, B=101
-- Active-low segments, in order a..g (0 to 6)
architecture Behavioral of SevenSegmentDecoder is
begin
  process (letter_in)
  begin
    case letter_in is
      when "001" =>  -- H
        segments_out <= "1001000";
      when "010" =>  -- E
        segments_out <= "0110000";
      when "011" =>  -- L
        segments_out <= "1110001";
      when "100" =>  -- O
        segments_out <= "0000001";
      when others => -- B: blank display
        segments_out <= "1111111";
    end case;
  end process;
end architecture Behavioral;

constant CLOCK_PERIOD : time := 5 ns;  -- Periodo del clock

BEGIN process
begin
  for i in 1 to 63 loop
    for j in 1 to 63 loop
      SW_TB(127 DOWNTO 64) <= std_logic_vector(to_signed(i, 64));
      SW_TB(63 DOWNTO 0) <= std_logic_vector(to_signed(j, 64));
      KEY_TB <= "11";
      wait for CLOCK_PERIOD;  -- Aspetta un fronte di clock per ogni coppia di valori
      KEY_TB <= "01";
      wait for CLOCK_PERIOD;
    end loop;
  end loop;
  wait;
end process;

DUT: rca_64bit port map(SW_TB, KEY_TB, LEDR_TB, HEX_TB);